Junior Scientist - Digital Design (f/m/d)

YOUR FUTURE RESPONSIBILITIES

• Implement digital IPs (e.g., accelerators for crypto algorithms for RISC-V platform), meeting schedule, area, power, and performance targets.
• Collaborate in developing precise design specifications for digital control blocks.
• Implement FSM’s and other control logic in System Verilog.
• Digital verification according to verification plans.
• Backend processing for FPGA and ASIC (synthesis, timing analysis, routing).
• Commitment to writing publications and attendance on relevant conferences.

YOUR PROFILE

• Master’s degree in Electrical Engineering, Computer Engineering or a similar field.
• RTL design fundamentals (Verilog and System-Verilog).
• Scripting languages (Tcl, Python, MATLAB, shell-scripting).
• Programming languages C++ or C.
• Basic experience with FPGA design tools.
• Knowledge of EDA tools for ASIC is a plus.
• Knowledge of Crypto algorithms and concepts is a plus.
• Oral and written English skills, German is a plus.

IMPORTANT FACTS ABOUT SAL

In the network of science and industry, SAL offers research in the areas of Sensor Systems, Intelligent Wireless Systems, Power Electronics and Embedded Systems. 
SAL – a great place to research.

• Diversified research activities with plenty of technical challenges.
• State-of-the-art lab facilities and instruments.
• Internal and external training opportunities for further development.
• Home Office possible.
• € 4 per day food allowance in restaurants or € 2 per day in supermarkets.
• Family & kids friendly.
• Free coffee/milk/tea & fresh fruits.
• Start of your employment: as soon as possible

This position is subject to the Collective Agreement for employees in non-university research (Research CA) in occupational group E1. For this position, your monthly salary will be EUR 3.520, paid 14 times a year.